IP core for Xilinx (Virtex and Zynq 7000), Microsemi (ProASIC3e), and NanoXplore (BRAVE) FPGAs. It can be used on a board with a single FPGA, or in a dual core hot-redundancy topology. Using two FPGAs on the same board, both IP cores receive telecommand, and send telemetry simultaneously. One of the FPGAs is the primary device and the other one is the secondary device. Only the telemetry sent by the primary device is forwarded to the transmitter (radio module). In case of a failure in the primary device, the secondary device becomes the primary. The error detection mechanism (in order to switch the primary and secondary devices) employs watchdog timers implemented in VHDL, as part of the IP core. At the board level (with the two FPGAs), there are also watchdog timers. In the VHDL implementation, there are error detection schemes based on encoding strategies, as part of the CCSDS recommendations. The following CCSDS encoding strategies have been implemented, and fully validated through certified test equipments:
- Reed-Solomon (RS);
- Reed-Solomon + Convolutional;
- Low-Density Parity-Check (LDPC).
There are three main options to buy this product:
Option A - Customer buys the binary (FPGA bitstream).
In this option, the customer buys the IP core in is binary format. This means that it just needs to be downloaded to a supported FPGA, but the customer you will need to make the proper modifications in the remaining software and hardware system components, in order to adapt them (and their interfaces) to our IP core.
Price: 10,000 euros
Option B - Customer buys the binary (FPGA bitstream), configured according to their system.
This is similar to option A, but instead of adapting your system to our IP core, we adapt our IP core to your system. Basically, the customer will have to provide to us the software and hardware components of it system, and we adapt the interfaces and functionality of our IP core accordingly.
Price: to be defined, depending on the amount of work to be performed.
Option C - Customer buys the VHDL source code.
We provide our full VHDL source code and, in this case, the customer you will be able to make modifications and the proper integration to its design.
Price: 100,000 euros